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Version 2.3, 8 May 2006
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CoolSETTM-F3 (Jitter Version)
ICE3 B03 6 5 J ICE3 B05 6 5 J ICE3 B15 6 5 J
Off-Line SMPS Current Mode Controller with integrated 650V Startup Cell/Depletion CoolMOSTM
Power Management & Supply
Never
stop
thinking.
CoolSETTM-F3 ICE3Bxx65J Revision History: Page
6, 8, 12, 13 11, 12
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2006-05-08
Datasheet
Previous Version: 2.2 ( ICE3B0365J/ICE3B0565J ), 2.0 ( ICE3B1565J ) Subjects (major changes since last revision)
Group ICE3B0365J, ICE3B0565J and ICE3B1565J together revise typo to the trigger level in Vsofts ( C2 ) and VFB ( C6a ) revise typo in figure 13 and 14
For questions on technology, delivery and prices please contact the Infineon Technologies Offices in Germany or the Infineon Technologies Companies and Representatives worldwide: see our webpage at http:// www.infineon.com CoolMOSTM, CoolSETTM are trademarks of Infineon Technologies AG.
Edition 2006-05-08 Published by Infineon Technologies AG 81726 Munchen, Germany
(c) Infineon Technologies AG 5/8/06. All Rights Reserved.
Attention please! The information given in this data sheet shall in no event be regarded as a guarantee of conditions or characteristics ("Beschaffenheitsgarantie"). With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
CoolSETTM-F3
ICE3Bxx65J
Off-Line SMPS Current Mode Controller with integrated 650V Startup Cell/Depletion CoolMOSTM Product Highlights
* Active Burst Mode to reach the lowest Standby Power Requirements < 100mW * Adjustable Blanking Window for High Load Jumps to increase Reliability * Frequency Jittering for Low EMI * Pb-free lead plating, RoHS compilant Features
* * * * * * * * * * * * * * * 650V Avalanche Rugged CoolMOSTM with built in switchable Startup Cell Active Burst Mode for lowest Standby Power @ light load controlled by Feedback Signal Fast Load Jump Response in Active Burst Mode 67 kHz fixed Switching Frequency Auto Restart Mode for Over temperature Detection Auto Restart Mode for Overvoltage Detection Auto Restart Mode for Overload and Open Loop Auto Restart Mode for VCC Undervoltage User defined Soft Start Minimum of external Components required Max Duty Cycle 75% Overall Tolerance of Current Limiting < 5% Internal Leading Edge Blanking BiCMOS technology provides wide VCC Range Frequency Jittering for Low EMI
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PG-DIP-8-6
test
Description
The CoolSETTM-F3(Jitter version) meets the requirements for Off-Line Battery Adapters and low cost SMPS for the lower power range. By use of a BiCMOS technology a wide VCC range up to 26V is provided. This covers the changes in the auxiliary supply voltage if a CV/CC regulation is implemented on the secondary side. Furthermore an Active Burst Mode is integrated to fullfill the lowest Standby Power Requirements <100mW at no load and Vin = 270VAC. As during Active Burst Mode the controller is always active there is an immediate response on load jumps possible without any black out in the SMPS. In Active Burst Mode the ripple of the output voltage can be reduced <1%. Furthermore Auto Restart Mode is entered in case of Overtemperature, VCC Overvoltage, Output Open loop or Overload and VCC Undervoltage. By means of the internal precise peak current limitation, the dimension of the transformer and the secondary diode can be lowered which leads to more cost efficiency.
Typical Application
+
85 ... 270 VAC
C Bulk C VCC
Snubber
Converter DC Output
-
VCC
Power Management PW M Controller Current Mode Precise Low Tolerance Peak Current Limitation Active Burst Mode Auto Restart Mode
Drain
Startup Cell
CS
Depl. CoolMOSTM
R Sense FB
GND
Control Unit
SoftS
CoolSETTM -F3 (Jitter Version)
C SoftS
Type
ICE3B0365J ICE3B0565J ICE3B1565J
1) 2)
Package
PG-DIP-8-6 PG-DIP-8-6 PG-DIP-8-6
Marking
ICE3B0365J ICE3B0565J ICE3B1565J
VDS
650V 650V 650V
FOSC
67kHz 67kHz 67kHz
RDSon1)
6.45 4.70 1.70
230VAC 15%2)
22W 25W 42W
85-265 VAC2)
10W 12W 20W
typ @ T=25C Calculated maximum input power rating at Ta=75C, Tj=125C and without copper area as heat sink
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Table of Contents Page 1 Pin Configuration and Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 1.1 Pin Configuration with PG-DIP-8-6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 1.2 Pin Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 2 3 3.1 3.2 3.3 3.4 3.4.1 3.4.2 3.4.3 3.5 3.5.1 3.5.2 3.6 3.6.1 3.6.2 3.6.2.1 3.6.2.2 3.6.2.3 3.6.3 3.6.3.1 4 4.1 4.2 4.3 4.3.1 4.3.2 4.3.3 4.3.4 4.3.5 4.3.6 5 6 7 8 Representative Blockdiagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Startup Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 PWM Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 PWM-Latch FF1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Gate Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Current Limiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Leading Edge Blanking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Propagation Delay Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Adjustable Blanking Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Active Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Entering Active Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Working in Active Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Leaving Active Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Protection Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Auto Restart Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Supply Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Internal Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 PWM Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Current Limiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 CoolMOSTM Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Temperature derating curve . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Outline Dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Schematic for recommended PCB layout . . . . . . . . . . . . . . . . . . . . . . . .24
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1
1.1
Pin 1 2 3 4 5 6 7 8
1)
Pin Configuration and Functionality
Pin Configuration with PG-DIP-8-6
1.2
Pin Functionality
Symbol SoftS FB CS Drain Drain N.C. VCC GND
Function Soft-Start Feedback Current Sense/ 650V1) Depl. CoolMOSTM Source 650V1) Depl. CoolMOSTM Drain 650V1) Depl. CoolMOSTM Drain Not Connected Controller Supply Voltage Controller Ground
SoftS (Soft Start, Auto Restart & Frequency Jittering Control) The SoftS pin combines the function of Soft Start during Start Up and error detection for Auto Restart Mode. These functions are implemented and can be adjusted by means of an external capacitor at SoftS to ground. This capacitor also provides an adjustable blanking window for high load jumps, before the IC enters into Auto Restart Mode. Furthermore this pin is also used to control the period of frequency jittering during normal load. FB (Feedback) The information about the regulation is provided by the FB Pin to the internal Protection Unit and to the internal PWM-Comparator to control the duty cycle. The FBSignal controls in case of light load the Active Burst Mode of the controller. CS (Current Sense) The Current Sense pin senses the voltage developed on the series resistor inserted in the source of the integrated Depl. CoolMOSTM. If CS reaches the internal threshold of the Current Limit Comparator, the Driver output is immediately switched off. Furthermore the current information is provided for the PWMComparator to realize the Current Mode. Drain (Drain of integrated Depl. CoolMOSTM) Pin Drain is the connection to the Drain of the internal Depl. CoolMOSTM. VCC (Power supply) The VCC pin is the positive supply of the IC. The operating range is between 10.3V and 26V. GND (Ground) The GND pin is the ground of the controller.
at Tj = 110C
Package PG-DIP-8-6
SoftS
1
8
GND
FB
2
7
VCC
CS
3
6
N.C
Drain
4
5
Drain
Figure 1 Note:
Pin Configuration PG-DIP-8-6(top view) Pin 4 and 5 are shorted within the DIP package.
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2
Figure 2
+ CBulk Snubber Converter DC Output VOUT CVCC
Version 2.3
VCC
5V Power Management Internal Bias Voltage Reference 5V Startup Cell
85 ... 270 VAC
Drain
Depl. CoolMOSTM
RSoftS
3.25k
SoftS GND
Undervoltage Lockout
18V 0.75 10.3V
T2
T3 Power-Down Reset Oscillator &
Duty Cycle max
0.8V
T1 PWM Section
CSoftS
Representative Blockdiagram
Spike Blanking 8.0us Soft Start Soft-Start Comparator
Clock Freq Jitter
VCC
C13
&
3V
20.5V
G12
SQ
UVLO
G13 Thermal Shutdown
Tj >140C
R
FF2
C7 Gate Driver & G9 1 G8 PWM Comparator C8 FF1 S RQ
S1
3.1V
C2
& G7
Representative Blockdiagram
6
& G5 Auto Restart Mode Propagation-Delay Compensation
0.6V
4.0V
C3
5V
RFB
4.5V
C4
25k & G6 C10 x3.2 PWM OP C12 & G11 Current Mode & G10 Active Burst Mode
FB
C5
10k 1pF D1
CS
RSense
2pF
1.35V
3.61V
C6a
Vcsth Leading Edge Blanking 220ns 0.32V
Control Unit
3.0V
C6b
Current Limiting
ICE3xxx65J / CoolSETTM- F3 Jitter version
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3
Functional Description
3.2
Drain Startup Cell
All values which are used in the functional description are typical values. For calculating the worst cases the min/max values which can be found in section 4 Electrical Characteristics have to be considered.
Power Management
VCC
3.1
Introduction
CoolSETTM-F3 Jitter version is the further development of the CoolSETTM-F2 to meet the requirements for the lowest Standby Power at minimum load and no load conditions. A new fully integrated Standby Power concept is implemented into the IC in order to keep the application design easy. Compared to CoolSETTM-F2 no further external parts are needed to achieve the lowest Standby Power. An intelligent Active Burst Mode is used for this Standby Mode. After entering this mode there is still a full control of the power conversion by the secondary side via the same optocoupler that is used for the normal PWM control. The response on load jumps is optimized. The voltage ripple on Vout is minimized. Vout is further on well controlled in this mode. The usually external connected RC-filter in the feedback line after the optocoupler is integrated in the IC to reduce the external part count. Furthermore a high voltage Startup Cell is integrated into the IC which is switched off once the Undervoltage Lockout on-threshold of 18V is exceeded. This Startup Cell is part of the integrated Depl. CoolMOSTM. The external startup resistor is no longer necessary as this Startup Cell is connected to the Drain. Power losses are therefore reduced. This increases the efficiency under light load conditions drastically. The Soft-Start capacitor is also used for providing an adjustable blanking window for high load jumps. During this time window the overload detection is disabled. With this concept no further external components are necessary to adjust the blanking window. An Auto Restart Mode is implemented in the IC to reduce the average power conversion in the event of malfunction or unsafe operating condition in the SMPS system. This feature increases the system's robustness and safety which would otherwise lead to a destruction of the SMPS. Once the malfunction is removed, normal operation is automatically initiated after the next Start Up Phase. The internal precise peak current limitation reduces the costs for the transformer and the secondary diode. The influence of the change in the input voltage on the power limitation can be avoided together with the integrated Propagation Delay Compensation. Therefore the maximum power is nearly independent on the input voltage which is required for wide range SMPS. There is no need for an extra over-sizing of the SMPS, e.g. the transformer or the secondary diode.
Power Management Internal Bias Undervoltage Lockout 18V 10.3
Power-Down Reset
Voltage Reference
5V
Auto Restart Mode Active Burst Mode
T1
SoftS
Figure 3 Power Management
The Undervoltage Lockout monitors the external supply voltage VVCC. When the SMPS is plugged to the main line the internal Startup Cell is biased and starts to charge the external capacitor CVCC which is connected to the VCC pin. The VCC charge current that is provided by the Startup Cell from the Drain pin is 1.05mA. When VVCC exceeds the on-threshold VCCon=18V, bias circuit is switched on. Then the Startup Cell is switched off by the Undervoltage Lockout and therefore no power losses present due to the connection of the Startup Cell to the Drain voltage. To avoid uncontrolled ringing at switch-on a hysteresis is implemented. The switch-off of the controller can only take place after active mode was entered and VVCC falls below 10.3V. The maximum current consumption before the controller is activated is about 300uA.
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When VVCC falls below the off-threshold VCCoff=10.3V the bias circuit is switched off and the Power Down reset let T1 discharging the soft-start capacitor CSoftS at pin SoftS. Thus it is ensured that at every startup cycle the voltage ramp at pin SoftS starts at zero. The bias circuit is switched off if Auto Restart Mode is entered. The current consumption is then reduced to 300uA. Once the malfunction condition is removed, this block will then turn back on. The recovery from Auto Restart Mode does not require disconnecting the SMPS from the AC line. When Active Burst Mode is entered, some internal Bias is switched off in order to reduce the current consumption to about 500uA while keeping a comparator (which trigger if VFB has exceeded 3.61V) and the Soft Start capacitor clamped at 3.0 V as this is necessary in this mode.
resistor RSoftS determines the duty cycle until VSoftS exceeds 3.1V. When the Soft Start begins, CSoftS is immediately charged up to approx. 0.8V by T2. Therefore the Soft Start Phase takes place between 0.8V and 3.1V. Above VSoftsS = 3.1V there is no longer duty cycle limitation DCmax which is controlled by comparator C7 since comparator C2 blocks the gate G7 (see Figure 5).This maximum charge current in the very first stage when VSoftS is below 0.8V, is limited to 0.9mA.
VSoftS
max. Startup Phase 4.0V 3.1V
0.8V
3.3
Startup Phase
3.25k RSoftS
max. Soft Start Phase
DCmax
5V
DC1 DC2
t
SoftS
CSoftS
Freq Jitter Charging current IFJ Freq Jitter Discharging current IFJ
T2 T3 0.8V Freq Jitter Control Soft-Start Comparator & G7 Gate Driver
t1
Figure 5 Startup Phase
t2 t
Soft Start C7
C2 3.1V PWM OP x3.2 0.6V CS
By means of this extra charge stage, there is no delay in the beginning of the Startup Phase when there is still no switching. Furthermore Soft Start is finished at 3.1V to have faster the maximum power capability. The duty cycles DC1 and DC2 are depending on the mains and the primary inductance of the transformer. The limitation of the primary current by DC2 is related to VSoftS = 3.1V. But DC1 is related to a maximum primary current which is limited by the internal Current Limiting with CS = 1V. Therefore the maximum Startup Phase is divided into a Soft Start Phase until t1 and a phase from t1 until t2 where maximum power is provided if demanded by the FB signal.
Figure 4
Soft Start
At the beginning of the Startup Phase, the IC provides a Soft Start duration whereby it controls the maximum primary current by means of a duty cycle limitation. A capacitor CSofts in combination with the internal pull up
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3.4
PWM Section
0.75 Oscillator Duty Cycle max Clock Frequency Jitter PWM Section
3.4.2 PWM-Latch FF1 The oscillator clock output provides a set pulse to the PWM-Latch when initiating the internal CoolMOSTM conduction. After setting the PWM-Latch can be reset by the PWM comparator, the Soft Start comparator or the Current-Limit comparator. In case of resetting the driver is shut down immediately. 3.4.3 Gate Driver The Gate Driver is a fast totem pole gate drive which is designed to avoid cross conduction currents. The Gate Driver is active low at voltages below the undervoltage lockout threshold VVCCoff.
Soft Start Comparator PWM Comparator Current Limiting
FF1 1 G8 S R Q Gate Driver & G9
VCC
PWM-Latch 1
SoftS
Figure 6 PWM Section
Gate
Gate Depl. CoolMOSTM
3.4.1 Oscillator and Jittering The oscillator generates a fixed frequency with frequency jittering of 4% from the fixed frequency (which is 2.7kHz from 67kHz) at a jittering period TFJ. The switching frequency is fswitch = 67kHz. A resistor, a capacitor and a current source and current sink which determine the frequency are integrated. The charging and discharging current of the implemented oscillator capacitor are internally trimmed, in order to achieve a very accurate switching frequency. The ratio of controlled charge to discharge current is adjusted to reach a maximum duty cycle limitation of Dmax=0.75. Once the Soft Start period is over and when the IC goes into normal mode, the Soft Start capacitor will be charged and discharged through internal current source, IFJ to generate a triangular waveform with a jittering period TFJ which is externally adjustable by the Soft Start capacitor, CSoftS (See Figure 4).
TFJ = kFJ * CSoftS where kFJ is a constant = 4 ms/uF eg. TFJ = 4 ms if CSoftS = 1uF
Gate Driver
Figure 7
Gate Driver
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3.5
PWM Latch FF1
Current Limiting
3.5.1
Leading Edge Blanking
VSense
Vcsth
Current Limiting
tLEB = 220ns
Propagation-Delay Compensation Vcsth C10 PWM-OP & G10 C12 0.32V 10k D1 1pF
t
Figure 9
Leading Edge Blanking 220ns
Leading Edge Blanking
Each time when the integrated internal CoolMOSTM is switched on a leading edge spike is generated due to the primary-side capacitances and secondary-side rectifier reverse recovery time. This spike can cause the gate drive to switch off unintentionally. To avoid a premature termination of the switching pulse, this spike is blanked out with a time constant of tLEB = 220ns. During this time, the gate drive will not be switched off.
Active Burst Mode
3.5.2
Propagation Delay Compensation
CS
Figure 8 Current Limiting
In case of overcurrent detection, the switch-off of the integrated internal CoolMOSTM is delayed due to the propagation delay of the circuit. This delay causes an overshoot of the peak current Ipeak which depends on the ratio of dI/dt of the peak current (see Figure 10).
There is a cycle by cycle Current Limiting realized by the Current-Limit comparator C10 to provide an overcurrent detection. The source current of the integrated Depl. CoolMOSTM is sensed via an external sense resistor RSense . By means of RSense the source current is transformed to a sense voltage VSense which is fed into the pin CS. If the voltage VSense exceeds the internal threshold voltage Vcsth the comparator C10 immediately turns off the gate drive by resetting the PWM Latch FF1. A Propagation Delay Compensation is added to support the immediate shut down without delay of the integrated internal CoolMOSTM in case of Current Limiting. The influence of the AC input voltage on the maximum output power can thereby be avoided. To prevent the Current Limiting from distortions caused by leading edge spikes a Leading Edge Blanking is integrated in the current sense path for the comparators C10, C12 and the PWM-OP. The output of comparator C12 is activated by the Gate G10 if Active Burst Mode is entered. Once activated the current limiting is thereby reduced to 0.32V. This voltage level determines the power level when the Active Burst Mode is left if there is a higher power demand.
Signal2 ISense Ipeak2 Ipeak1 ILimit IOvershoot2
Signal1 tPropagation Delay
IOvershoot1
t
Figure 10 Current Limiting The overshoot of Signal2 is bigger than of Signal1 due to the steeper rising waveform. This change in the slope is depending on the AC input voltage. Propagation Delay Compensation is integrated to limit the overshoot dependency on dI/dt of the rising primary current. That means the propagation delay time between exceeding the current sense threshold Vcsth and the switch off of the integrated inernal CoolMOSTM is compensated over temperature within a wide range.
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Current Limiting is now possible in a very accurate way. E.g. Ipeak = 0.5A with RSense = 2. Without Propagation Delay Compensation the current sense threshold is set to a static voltage level Vcsth=1V. A current ramp of dI/dt = 0.4A/s, that means dVSense/dt = 0.8V/s, and a propagation delay time of i.e. tPropagation Delay =180ns leads then to an Ipeak overshoot of 14.4%. By means of propagation delay compensation the overshoot is only about 2% (see Figure 11).
with compensation without compensation
3.6
Control Unit
V
1,3 1,25 1,2
The Control Unit contains the functions for Active Burst Mode and Auto Restart Mode. The Active Burst Mode and the Auto Restart Mode are combined with an Adjustable Blanking Window which is depending on the external Soft Start capacitor. By means of this Adjustable Blanking Window, the IC avoids entering into these two modes accidentally. Furthermore it also provides a certain time whereby the overload detection is delayed. This delay is useful for applications which normally works with a low current and occasionally require a short duration of high current.
3.6.1
Adjustable Blanking Window
VSense
1,15 1,1 1,05 1 0,95 0,9 0 0,2 0,4 0,6 0,8 1 1,2 1,4 1,6 1,8 2
SoftS
S3 RSoftS Frequency Jitter
5V
dVSense dt
V s
3.0V S1
S2
Figure 11
Overcurrent Shutdown
The Propagation Delay Compensation is realized by means of a dynamic threshold voltage Vcsth (see Figure 12). In case of a steeper slope the switch off of the driver is earlier to compensate the delay.
4.0V
C3
VOSC
max. Duty Cycle
4.5V C4
off time
& G5
Auto Restart Mode
VSense Vcsth
Propagation Delay
t
Active Burst Mode & G6 C5 1.35V Control Unit
FB
Signal1
Figure 12
Signal2
t
Figure 13
Adjustable Blanking Window
Dynamic Voltage Threshold Vcsth
VSoftS swings between 3.2V and 3.6V after the SMPS is settled and S2 is on while S3 is off, this is due to the frequency jittering function that is making use of the Soft Start pin. If overload occurs VFB is exceeding 4.5V. Auto Restart Mode can't be entered as the gate G5 is still blocked by the comparator C3. But after VFB has
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exceeded 4.5V the switch S2 is opened and S3 is closed. The external Soft Start capacitor can now be charged further by the integrated pull up resistor RSoftS via switch S3. The comparator C3 releases the gates G5 and G6 once VSofts has exceeded 4.0V. Therefore there is no entering of Auto Restart Mode possible during this charging time of the external capacitor CSoftS. The same procedure happens to the external Soft Start capacitor if a low load condition is detected by comparator C5 when VFB is falling below 1.35V. Only after VSoftS has exceeded 4.0V and VFB is still below 1.35V Active Burst Mode is entered.
The Active Burst Mode is located in the Control Unit. Figure 14 shows the related components.
3.6.2 Active Burst Mode The controller provides Active Burst Mode for low load conditions at VOUT. Active Burst Mode increases significantly the efficiency at light load conditions while supporting a low ripple on VOUT and fast response on load jumps. During Active Burst Mode which is controlled only by the FB signal the IC is always active and can therefore immediately response on fast changes at the FB signal. The Startup Cell is kept switched off to avoid increased power losses for the self supply.
SoftS
S3 5V RSoftS Frequency Jitter
3.0V
S2
3.6.2.1 Entering Active Burst Mode The FB signal is always observed by the comparator C5 if the voltage level falls below 1.35V. In that case the switch S1 and S2 is released which allows the capacitor CSoftS to be charged via S3 starting from the swinging voltage level between 3.2V and 3.6V in normal operating mode. If VSoftS exceeds 4.0V the comparator C3 releases the gate G6 to enter the Active Burst Mode. The time window that is generated by combining the FB and SoftS signals with gate G6 avoids a sudden entering of the Active Burst Mode due to large load jumps. This time window can be adjusted by the external capacitor CSoftS. After entering Active Burst Mode a burst flag is set and the internal bias is switched off in order to reduce the current consumption of the IC down to approx. 500uA. Also, switch S1 is closed to clamped the Soft Start voltage to 3.0V. In this Off State Phase the IC is no longer self supplied so that therefore CVCC has to provide the VCC current (see Figure 15). Furthermore gate G11 is then released to start the next burst cycle once VFB has 3.0V exceeded. It has to be ensured by the application that the VCC remains above the Undervoltage Lockout Level of 10.3V to avoid that the Startup Cell is accidentally switched on. Otherwise power losses are significantly increased. The minimum VCC level during Active Burst Mode is depending on the load conditions and the application. The lowest VCC level is reached at no load conditions at VOUT. 3.6.2.2 Working in Active Burst Mode After entering the Active Burst Mode the FB voltage rises as VOUT starts to decrease due to the inactive PWM section. Comparator C6a observes the FB signal if the voltage level 3.61V is exceeded. In that case the internal circuit is again activated by the internal Bias to start with switching. As now in Active Burst Mode the gate G10 is released the current limit is only 0.32V to reduce the conduction losses and to avoid audible noise. If the load at VOUT is still below the starting level for the Active Burst Mode the FB signal decreases down to 3.0V. At this level C6b deactivates again the internal circuit by switching off the internal Bias. The gate G11 is released as after entering Active Burst Mode the burst flag is set. If working in Active Burst Mode the FB voltage is changing like a saw tooth between 3.0V and 3.61V (see figure 15). 3.6.2.3 Leaving Active Burst Mode The FB voltage immediately increases if there is a high load jump. This is observed by comparator C4. As the current limit is ca. 32% during Active Burst Mode a certain load jump is needed that FB can exceed 4.5V. At this time C4 resets the Active Burst Mode which also
S1
Internal Bias Current Limiting & G10
C3 4.0V 4.5V C4
FB
1.35V
C5
& G6
Active Burst Mode
C6a 3.61V
C6b 3.0V Control Unit
& G11
Figure 14
Active Burst Mode
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blocks C12 by the gate G10. Maximum current can now be provided to stabilize VOUT.
VFB
4.5V 3.61V 3.0V 1.35V
3.6.3 Protection Modes The IC provides several protection features that increase the SMPS system's robustness and safety. The following table shows the possible system failures and the corresponding protection modes.
VCC Overvoltage Over temperature Overload Open Loop VCC Undervoltage Short Optocoupler Auto Restart Mode I Auto Restart Mode I Auto Restart Mode II Auto Restart Mode II Auto Restart Mode II Auto Restart Mode II
Entering Active Burst Mode
Leaving Active Burst Mode
VSoftS
Blanking Window 4.0V 3.6V~ 3.2V 3.0V
t
3.6.3.1
Auto Restart Mode I
VCS
1.0V 0.32V Current limit level during Active Burst Mode
t
SoftS
C3 4.0V S UVLO RQ FF2 Auto Restart Mode & G13 Spike Blanking 8.0us C13 20.5V
t
VVCC
t
VCC
10.3V
& G12
IVCC
2mA
C4 4.5V Thermal Shutdown
Internal Bias
500uA
Tj >140C
t Max. Ripple < 1%
Control Unit
VOUT
FB
Figure 16 Auto Restart Mode I
t
The VCC voltage is observed by comparator C13 if 20.5V is exceeded. The output of C13 is combined with both the output of C3 which checks for VSoftS < 4.0V and the output of C4 which checks for VFB > 4.5V. Therefore the overvoltage detection can only be active during Soft Start Phase (VSoftS < 4.0V) and when FB signal is outside the operating range > 4.5V. This means any
Figure 15
Signals in Active Burst Mode
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small voltage overshoots of VVCC during normal operating cannot trigger the Auto Restart Mode I. In Order to ensure system reliability and prevent any false activation, a blanking time is implemented before the IC can enter into the Auto Restart Mode I. The output of the VCC overvoltage detection is fed into a spike blanking with a time constant of 8.0us. The other fault detection which can result in the Auto Restart Mode I and has this 8.0us blanking time is the Overtemperature detection. This block checks for a junction temperature of higher than 140C for malfunction operation. Once Auto Restart Mode is entered, the internal bias is switched off in order to reduce the current consumption of the IC as much as possible. In this mode, the average current consumption is only 300uA as the only working blocks are the reference block and the Undervoltage Lockout(UVLO) which controls the Startup Cell by switching on/off at VVCCon/VVCCoff. As there is no longer a self supply by the auxiliary winding, VCC starts to drop. The UVLO switches on the integrated Startup Cell when VCC falls below 10.3V. It will continue to charge VCC up to 18V whereby it is switched off again and the IC enters into the Start Up Phase. As long as all fault conditions have been removed, the IC will automatically power up as usual with switching cycle at the GATE output after Soft Start duration. Thus the name Auto Restart Mode.
This charging of the Soft Start capacitor from 3.2V~3.6V to 4.0V defines a blanking window which prevents the system from entering into Auto Restart Mode II unintentionally during large load jumps. In this event, FB will rise close to 5.0V for a short duration before the loop regulates with FB less than 4.5V. This is the same blanking time window as for the Active Burst Mode and can therefore be adjusted by the external CSoftS. In case of VCC undervoltage, ie. VCC falls below 10.3V, the IC will be turned off with the Startup Cell charging VCC as described earlier in this section. Once VCC is charged above 18V, the IC will start a new startup cycle. The same procedure applies when the system is under Short Optocoupler fault condition, as it will lead to VCC undervoltage.
3.6.3.2
Auto Restart Mode II
SoftS
C3 4.0V 4.5V C4 & G5
Internal Bias
Auto Restart Mode
FB
Control Unit
Figure 17
Auto Restart Mode II
In case of Overload or Open Loop, FB exceeds 4.5V which will be observed by C4. At this time, the external Soft Start capacitor can now be charged further by the integrated pull up resistor RSoftS via switch S3 (see Figure 13). If VSoftS exceeds 4.0V which is observed by C3, Auto Restart Mode II is entered as both inputs of the gate G5 are high.
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4
Note:
Electrical Characteristics
All voltages are measured with respect to ground (Pin 8). The voltage levels are valid if other ratings are not violated.
4.1
Note:
Absolute Maximum Ratings
Absolute maximum ratings are defined as ratings, which when being exceeded may lead to destruction of the integrated circuit. For the same reason make sure, that any capacitor that will be connected to pin 7 (VCC) is discharged before assembling the application circuit.
Parameter
Drain Source Voltage Pulse drain current, tp limited by max. Tj=150C Avalanche energy, repetitive tAR limited by max. Tj=150C1) Avalanche current, repetitive tAR limited by max. Tj=150C1) VCC Supply Voltage FB Voltage SoftS Voltage CS Voltage Junction Temperature Storage Temperature Thermal Resistance Junction-Ambient ESD Capability
1) 2)
Symbol
VDS ICE3B0365J ICE3B0565J ICE3B1565J ICE3B0365J ICE3B0565J ICE310565J ICE3B0365J ICE3B0565J ICE3B1565J ID_Puls1 ID_Puls2 ID_Puls3 EAR1 EAR2 EAR3 IAR1 IAR2 IAR3 VVCC VFB VSoftS VCS Tj TS RthJA VESD -
Limit Values min. max.
650 0.9 1.6 6.1 0.005 0.01 0.15 0.3 0.5 1.5 27 5.0 5.0 5.0 150 150 90 2
Unit
V A A A mJ mJ mJ A A A V V V V C C K/W kV
Remarks
Tj = 110C
-0.3 -0.3 -0.3 -0.3 -40 -55 -
Controller & CoolMOSTM PG-DIP-8-6 Human body model2)
Repetetive avalanche causes additional power losses that can be calculated as PAV=EAR* f According to EIA/JESD22-A114-B (discharging a 100pF capacitor through a 1.5k series resistor)
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4.2
Note:
Operating Range
Within the operating range the IC operates as described in the functional description.
Parameter
VCC Supply Voltage Junction Temperature of Controller Junction Temperature of CoolMOSTM
Symbol
VVCC TjCon TJCoolMOS
Limit Values min.
VVCCoff -25 -25
Unit
V C C
Remarks
max.
26 130 150 Max value limited due to integrated thermal shut down
4.3
4.3.1 Note:
Characteristics
Supply Section The electrical characteristics involve the spread of values guaranteed within the specified supply voltage and junction temperature range TJ from - 25 oC to 130 oC. Typical values represent the median values, which are related to 25C. If not otherwise stated, a supply voltage of VCC = 18 V is assumed. Symbol min.
IVCCstart IVCCcharge1 IVCCcharge2 IVCCcharge3 0.55 1.05 0.88 0.2 1.7 2.5 300 -
Parameter
Start Up Current VCC Charge Current
Limit Values typ.
300
Unit
A mA mA mA A mA mA A
Test Condition
VVCC = 17V VVCC = 0V VVCC = 1V VVCC = 17V VDrain= 450V at Tj = 100C Soft Start pin is open VSoftS = 3.0V IFB = 0 IFB = 0 ISofts = 0 VFB = 2.5V VSoftS = 3.0V VVCC = 11.5V VFB = 2.5V VSoftS = 3.0V
max.
450 5.0 1.60 50 2.5 3.6 -
Leakage Current of Start Up Cell & CoolMOS Supply Current with Inactive Gate
IStartLeak IVCCsup_ng
Supply Current with Active Gate IVCCsup_g Supply Current in Auto Restart Mode with Inactive Gate Supply Current in Active Burst Mode with Inactive Gate IVCCrestart
IVCCburst1 IVCCburst2
-
500 500
950 950
uA uA
VCC Turn-On Threshold VCC Turn-Off Threshold VCC Turn-On/Off Hysteresis
VVCCon VVCCoff VVCChys
17.0 9.6 -
18.0 10.3 7.7
19.0 11.0 -
V V V
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4.3.2
Internal Voltage Reference Symbol min.
VREF 4.90
Parameter
Trimmed Reference Voltage
Limit Values typ.
5.00
Unit
V
Test Condition
measured at pin FB IFB = 0
max.
5.10
4.3.3 Parameter
PWM Section Symbol min.
fOSC3 fOSC4 fdelta Dmax Dmin AV VMax-Ramp 58 62 0.70 0 3.0 9 30
Limit Values typ.
67 67 2.7 0.75 3.2 0.6 0.5 14 45
Unit
kHz kHz kHz
Test Condition
max.
76 74.5 0.80 3.4 4.3 22 62 V V V k k CS=1V limited by Comparator C41) VFB < 0.3V Tj = 25C Tj = 25C
Fixed Oscillator Frequency Frequency Jittering Range Max. Duty Cycle Min. Duty Cycle PWM-OP Gain Max. Level of Voltage Ramp
VFB Operating Range Min Level VFBmin VFB Operating Range Max level VFBmax Feedback Pull-Up Resistor Soft-Start Pull-Up Resistor
1)
RFB RSoftS
This parameter is not subject to production test - verified by design/characterization
4.3.4 Parameter
Control Unit Symbol min.
VSoftSC2 2.98
Limit Values typ.
3.10 3.00 4.00 0.9 4.50
Unit
V V V mA V
Test Condition
VFB = 5V
max.
3.22 3.12 4.15 4.67
Deactivation Level for SoftS Comparator C7 by C2 Clamped VSoftS Voltage during Burst Mode Activation Limit of Comparator C3 SoftS Startup Current Over Load & Open Loop Detection Limit for Comparator C4 Active Burst Mode Level for Comparator C5 Active Burst Mode Level for Comparator C6a
VSoftSclmp_bm 2.88 VSoftSC3 ISoftSstart VFBC4 3.85 4.33
VFB = 5V VSoftS = 0V VSoftS = 4.5V
VFBC5 VFBC6a
1.23 3.48
1.35 3.61
1.43 3.76
V V
VSoftS = 4.5V After Active Burst Mode is entered
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Active Burst Mode Level for Comparator C6b Overvoltage Detection Limit Thermal Shutdown Spike Blanking
1) 1)
VFBC6b VVCCOVP TjSD tSpike
2.88 19.5 130 -
3.00 20.5 140 8.0
3.12 21.5 150 -
V V C s
After Active Burst Mode is entered VFB = 5V, VSoftS = 3V
The parameter is not subject to production test - verified by design/characterization The trend of all the voltage levels in the Control Unit is the same regarding the deviation except VVCCOVP
Note:
4.3.5 Parameter
Current Limiting Symbol min.
Vcsth 1.01
Limit Values typ.
1.06
Unit
V
Test Condition
dVsense / dt = 0.6V/s
max.
1.11
Peak Current Limitation (incl. Propagation Delay Time) (see Figure 11) Peak Current Limitation during Active Burst Mode Leading Edge Blanking CS Input Bias Current
VCS2 tLEB ICSbias
0.27 -1.0
0.32 220 -0.2
0.37 0
V ns A VSoftS = 3.0V VCS = 0V
4.3.6 Parameter
CoolMOSTM Section
Symbol min.
V(BR)DSS RDSon1 600 650 -
Limit Values typ.
6.45 13.70 4.70 10.00 1.70 3.57 3.65 4.75 11.63 30
2)
Unit
V V pF pF pF ns ns
Test Condition
Tj = 25C Tj = 110C Tj = 25C Tj = 125C1) at ID = 0.3A Tj = 25C Tj = 125C1) at ID = 0.5A Tj = 25C Tj = 125C1) at ID = 1.5A VDS = 0V to 480V
max.
7.50 17.00 5.44 12.50 1.96 4.12 -
Drain Source Breakdown Voltage Drain Source On-Resistance ICE3B0365J
ICE3B0565J
RDSon2
ICE3B1565J
RDSon3
Effective output capacitance, energy related Rise Time Fall Time
1) 2)
ICE3B0365J ICE3B0565J ICE3B1565J
Co(er)1 Co(er)2 Co(er)3 trise tfall
302)
The parameter is not subject to production test - verified by design/characterization Measured in a Typical Flyback Converter Application
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Temperature derating curve
Safe Operating Area for ICE3A(B)0365(J) ID = f ( VDS ) parameter : D = 0, TC = 25deg.C 10
1
ID [A]
0.1
0.01
tp = tp = tp = tp = tp = DC
0.01ms 0.1ms 1ms 10ms 100ms
0.001 1 10 V DS [V] 100 1000
Figure 18 Safe Operating area ( SOA ) curve for ICE3B0565J
Safe Operating Area for ICE3A(B)0565(J) ID = f ( VDS ) parameter : D = 0, TC = 25deg.C 10
1
ID [A]
0.1
0.01
tp = tp = tp = tp = tp = DC
0.1ms 1ms 10ms 100ms 1000ms
0.001 1 10 V DS [V] 100 1000
Figure 19 Safe Operating area ( SOA ) curve for ICE3B0565J
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Safe Operating Area for ICE3A(B)1565(J) ID = f ( VDS ) parameter : D = 0, TC = 25deg.C 10
1
ID [A]
0.1
0.01
tp = tp = tp = tp = tp = DC
0.1ms 1ms 10ms 100ms 1000ms
0.001 1 10 V DS [V] 100 1000
Figure 20 Safe Operating area ( SOA ) curve for ICE3B1565J
SOA temperature derating coefficient curve for F3 & F2 CoolSET
120
SOA temperature derating coefficient [%]
100
80
60
40
20
0 0 20 40 60 80 100 120 140 Junction temperature Tc [deg.C]
Figure 21 SOA temperature derating coefficient curve
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6
Outline Dimension
PG-DIP-8-6 (Plastic Dual In-Line Outline)
Figure 22 PG-DIP-8-6 ( Pb-free lead plating Platic Dual-in-Line Outline )
Dimensions in mm
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Marking
Marking
Figure 23 Marking for ICE3B0365J Marking
Figure 24 Marking for ICE3B0565J
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Marking
Figure 25 Marking for ICE3B1565J
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Schematic for recommended PCB layout
8
Schematic for recommended PCB layout
TR1
BR1 Spark Gap 3 FUSE1
R11 C11 bulk cap D11
C12
D21
L
Spark Gap 1
X-CAP C1 L1
Vo
C21
GND
Spark Gap 2 Spark Gap 4 C2 Y-CAP C3 Y-CAP C4 Y-CAP SOFTS/BL GND C13 R12 CS D11 Z11
GND
C16 R21
N
IC11
DRAIN R13 R14 D13
F3 CoolSET VCC
FB C15 NC
R23
R22 C22
*
C14
C23
R24
IC12
IC21 R25
F3 CoolSET schematic for recommended PCB layout
Figure 26 Schematic for recommended PCB layout
General guideline for PCB layout design using F3 CoolSET (refer to Figure 26): 1. "Star Ground "at bulk capacitor ground, C11: "Star Ground "means all primary DC grounds should be connected to the ground of bulk capacitor C11 separately in one point. It can reduce the switching noise going into the sensitive pins of the CoolSET device effectively. The primary DC grounds include the followings. a. DC ground of the primary auxiliary winding in power transformer, TR1, and ground of C16 and Z11. b. DC ground of the current sense resistor, R12 c. DC ground of the CoolSET device, GND pin of IC11; the signal grounds from C13, C14, C15 and collector of IC12 should be connected to the GND pin of IC11 and then "star "connect to the bulk capacitor ground. d. DC ground from bridge rectifier, BR1 e. DC ground from the bridging Y-capacitor, C4 2. High voltage traces clearance: High voltage traces should keep enough spacing to the nearby traces. Otherwise, arcing would incur. a. 400V traces (positive rail of bulk capacitor C11) to nearby trace: > 2.0mm b. 600V traces (drain voltage of CoolSET IC11) to nearby trace: > 2.5mm 3. Filter capacitor close to the controller ground: Filter capacitors, C13, C14 and C15 should be placed as close to the controller ground and the controller pin as possible so as to reduce the switching noise coupled into the controller. Guideline for PCB layout design when >3KV lightning surge test applied (refer to Figure 26): 1. Add spark gap Spark gap is a pair of saw-tooth like copper plate facing each other which can discharge the accumulated charge during surge test through the sharp point of the saw-tooth plate. a. Spark Gap 3 and Spark Gap 4, input common mode choke, L1: Gap separation is around 1.5mm (no safety concern)
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Schematic for recommended PCB layout
b. Spark Gap 1 and Spark Gap 2, Live / Neutral to GROUND: These 2 Spark Gaps can be used when the lightning surge requirement is >6KV. 230Vac input voltage application, the gap separation is around 5.5mm 115Vac input voltage application, the gap separation is around 3mm 2. Add Y-capacitor (C2 and C3) in the Live and Neutral to ground even though it is a 2-pin input 3. Add negative pulse clamping diode, D11 to the Current sense resistor, R12: The negative pulse clamping diode can reduce the negative pulse going into the CS pin of the CoolSET and reduce the abnormal behavior of the CoolSET. The diode can be a fast speed diode such as IN4148. The principle behind is to drain the high surge voltage from Live/Neutral to Ground without passing through the sensitive components such as the primary controller, IC11.
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